The most widely used electrically-erasable, electrically-programmable, read-only cell is an n-channel field effect transistor with an additional floating gate structure disposed between the channel and the control gate. By charging the floating gate with electrons, a logic "zero" can be programmed into the cell, while allowing the floating gate to remain uncharged programs a logic "one." This is due to the fact that the charge on the floating gate controls the conductance of the underlying channel area, thereby determining whether a current will be sensed between the source and the drain when reading voltages are applied therebetween.
As in the case of the conventional field effect transistor, the channel of a EEPROM cell with an uncharged floating gate (a non-programmed cell) has a threshold voltage V.sub.t. This threshold voltage V.sub.t is primarily a function of the material used to form the channel and can be controlled within limits by the implantation of dopants in the channel during the fabrication of the cell. During the read operation, the control gate must be brought to a potential in excess of the threshold voltage V.sub.t, as determined by the capacitive coupling between the control gate and the floating gate and floating gate and the channel, in order for current to flow between the source and the drain when a voltage potential is created between them. By charging the floating gate with electrons, however, the threshold voltage V.sub.t can be raised.
One means of effecting the charging of the floating gate is through Fowler-Nordheim tunneling. In the n-channel EEPROM, when the control gate is brought to a sufficiently high potential in relationship to the drain, electrons can be made to tunnel through a thin oxide tunneling region adjacent the drain to the floating gate, thereby charging it. By raising the threshold voltage by charging the floating gate, a logic "zero" is programmed into the cell due to the fact that the normal reading voltage applied to the control gate will not exceed the potential necessary to allow the current flow in the channel as raised by the charged floating gate, and therefore no current can be sensed when proper source and drain reading voltages are applied.
In principle, it is possible to set the threshold voltage of a EEPROM to any value by varying the amount of charge residing on the floating gate. This may be done, for instance, by varying the pulse height, duration and/or the number of pulses used in creating the voltage potential between the control gate and the drain. In practice, however, this is not an easy task. First, the threshold voltage has a logarithmic dependency on pulse duration. Further, this process is very slow, requiring unacceptable expenditures of time to program the cell to extreme values. Additionally, variations from cell to cell, especially due to differences in the tunnel oxides used for Fowler-Nordheim tunneling, create consistency problems during array operation. Finally, trapping of materials in the oxide will change the current-voltage (I-V) characteristics of the tunnel diode over time, which may require frequent calibration cycles to determine the write/erase characteristics of the EEPROM cell.
A self-limiting erase scheme for an EEPROM cell is disclosed in U.S. Pat. No. 4,797,856. This device will allow the floating gate of an EEPROM cell to be erased to a predetermined value, thus controlling the threshold voltage of the cell. This device has a major disadvantage if it is ever desired to set the threshold voltage of an unprogrammed cell. In this case, the floating gate would have to be completely charged, and then erased back to a point where the charge remaining on the floating gate set the threshold voltage of the cell to the desired value.
Thus, a need has arisen for an electrically-erasable read only memory cell in which the threshold voltage of the channel can be set either during the write cycle or the erase cycle. Such a device would be self-controlling, and would minimize the need for precise controlling of the voltage application during the write and erase cycles. Further, this device should be capable of fabrication into an integrated circuit form using conventional techniques Finally, the device should be compatible with the peripheral devices currently used with EEPROM cells.